This invention relates to high density, high performance, semiconductor arrays of memory, and in particular to complementary bipolar transistor memory cells.
It is well known in the art that although a bipolar transistor's emitter and collector terminals may be swapped, the emitter and collector terminals are not functionally equivalent. A transistor with its base to emitter junction forward biased and base to collector junction reversed biased exhibits a high current amplification. The same transistor with its emitter and collector swapped, i.e., its base to collector junction forward biased and its base to emitter junction reverse biased, exhibits much lower current amplification. The first biasing condition is the transistor's normal mode of operation and the second biasing condition is the transistor's inverse mode of operation. Transistors operating in their inverse mode are known as inverse mode or inversion mode transistors.
In Merged Transistor Logic (MTL) memory cell design inverse mode transistors were used in the prior art. Inverse mode transistors were used because, the cell's cross coupled transistors could be made much smaller as inverse mode transistors than as normal mode transistors. Vertical transistors have small emitters on and surrounded by a base region and the base region is on and surrounded by a much larger collector region. Because isolating transistor collectors means significantly expanding transistor area, inversion mode transistors were used for cross coupled transistors with a common emitter connection. Although these cross-coupled transistors were schematically represented as normal mode transistors, it was understood and described in the prior art that the cross coupled transistors in merged transistor memory cells were inversion mode transistors. Efficient use of space is especially important in memory cell design because chip size is directly proportional to cell size. A 10% reduction in cell size will translate to nearly a 10% reduction in chip size. A 10% reduction in chip size translates to 11% increase in the number of chips per wafer and, because wafer cost is generally independent of number of chips on the wafer, memory chip cost is reduced. However, reducing size by using inverse mode transistors meant that, because inversion mode transistors are slow, these merged transistor memory cells were slow.
A high performance alternative to the merged transistor cell was the complementary transistor switch (CTS) cell of U.S. Pat. No. 3,863,229 incorporated herein by reference. Essentially, the CTS cell was a pair of cross coupled PNPN switching devices (silicon controlled rectifier or SCR). Each SCR has a Schottky Barrier Diode (SBD) across the second PN junction (between the SCR's control gates). The SBD prevents saturation of the NPN and PNP transistors which are intrinsic to the SCR structure. That the current limiting SBD's could be eliminated was disclosed in "saturated CTS Memory Cell Using A PNP Load", IBM Technical Disclosure Bulletin Vol. 26 No. 9, Feb. 1984, pp 4720-21.
While the CTS cell improved read access performance over the merged transistor cell without sacrificing cell density, the CTS cell still suffered from a slow cell write time. Cell write time was slow for 2 reasons. First, when a SCR is turned on, both intrinsic transistors are in deep saturation. As a result, the junction capacitances are high. Second, writing the cell is done by pulling one side of the cell high, i.e., by supplying enough current to the collector of the intrinsic NPN transistor in the "ON" SCR to pull that NPN transistor far enough out of saturation to switch the "OFF" SCR on. Even after the "OFF" SCR has been switched on, the CTS cell still has not been written The "OFF" SCR must have been switched on long enough to turn the "ON" SCR off. Switching time required to switch the CTS cell is further impaired because the junction capacitance of the "ON" SCR (which is in deep saturation) is high. High junction capacitance means stored charge is high Since discharge time for any given discharge current is directly related to the amount of stored charge, increased stored charge means increased discharge (write) time. So, because writing the CTS memory cell requires the time it takes to pull one side of the cell high, thereby turning on the "OFF" SCR, and pull the other side low, thereby turning off the "ON" SCR, the CTS write time is slow.
A second problem encountered with the CTS cell which arose from an attempt to improve CTS write time was intolerance to leakage from the intrinsic PNP transistors. In order to improve write time, the current gain of the SCR's intrinsic PNP and NPN transistors was weakened. Weakening the intrinsic transistors made the cell easier to write because the ON SCR's weakened transistors were not as deeply in saturation. So, weakening the transistors produced the same effect as the SBD's in early CTS cells. However, a cell which is easier to write is often easier to upset or disturb and is, therefore, less stable. Leakage problems occurred because of leakage between the high side of cell and the substrate. As a result of weakening the SCRs, the SCR's functions became leakier. While leakage in the PN junction between the P type substrate and the base of the PNP transistor in the "ON" SCR merely reinforced the low level on the base of "ON" SCR's intrinsic PNP transistor, leakages in the PN junction between the P type substrate and the base of the PNP transistor in the "OFF" SCR had the opposite effect The leakage in the intrinsic PNP transistor base of the "OFF" transistor pulled the cell's high side down, reducing the levels stored in the cell, making the cell easier to upset or disturb, and therefore, even less stable Consequently the CTS cell was more sensitive to read disturb, soft errors and other noise.
Read disturbs occur when, in an attempt to read the data stored in the cell, the cell is upset. Soft errors are errors induced into a memory chip when a memory cell is upset by its environment, such as by being upset when PN junction in the cell is struck by an alpha particle. Memory cell designers were thus faced, with trading performance for density and stability; stability for performance and density; or, density for performance and stability.